A current multiplication circuit using a current mirror circuit has been widely used as a constant current circuit for use of a bias circuit requiring a large output current or an active load. A conventional current multiplication circuit is disclosed in Japanese Patent Publication (Kokai) No. 11-234135.
In the current multiplication circuit disclosed in the Publication, a plurality of output transistors of a current mirror circuit are connected in parallel so that the output current may have a desired value.
In a portable device typified by a cellular phone, it has been required at a transmission output stage that a bias current circuit covers an output current (a bias current) having a dynamic range of two to three digits. Furthermore, in such an application, there is a limitation that, in order to suppress switching noises to be produced at the time a bias current is switched, it is necessary to avoid turning on and off a plurality of output transistors of a bias current circuit simultaneously. Therefore, it is difficult to adopt a decode system to select an output transistor, so that it is necessary to connect output transistors of the number equivalent to required current steps in parallel.
However, in the conventional current multiplication circuit as described above, there has been an essential problem that a layout area increases in proportion to a ratio of an output current to a reference current. Particularly, a problem arises in the case where the output transistors connected in parallel are selected sequentially by means of switches in order to suppress the switching noises. The problem is that the layout area increases to the extent that the bias current circuit occupies a large portion of a core circuit, when the bias current circuit covers a wide dynamic range, for example, several hundreds μA to several tens mA.